A 21 fJ/Conversion-Step 100 kS/s 10-bit ADC With a Low-Noise Time-Domain Comparator for Low-Power Sensor Interface.
Seon-Kyoo LeeSeung-Jin ParkHong-June ParkJae-Yoon SimPublished in: IEEE J. Solid State Circuits (2011)
Keyphrases
- low power
- analog to digital converter
- image sensor
- power consumption
- mixed signal
- wide dynamic range
- low cost
- low power consumption
- high speed
- single chip
- cmos image sensor
- high power
- vlsi circuits
- energy dissipation
- digital signal processing
- cmos technology
- frequency domain
- logic circuits
- power reduction
- signal to noise ratio
- signal processor
- multi channel
- real time
- ultra low power
- wireless transmission
- delay insensitive
- noise model
- gaussian noise
- sensor networks