Instruction scheduling for a clustered VLIW processor with a word-interleaved cache.
Enric GibertF. Jesús SánchezAntonio GonzálezPublished in: Concurr. Comput. Pract. Exp. (2006)
Keyphrases
- instruction scheduling
- multithreading
- parallel computing
- cache misses
- computational power
- highly efficient
- constraint programming
- level parallelism
- embedded processors
- multi core processors
- co occurrence
- memory subsystem
- word sense disambiguation
- processor core
- memory efficient
- memory access
- real time
- database workloads
- computational complexity
- shared memory multiprocessor
- data partitioning
- distributed memory
- coarse grained
- prefetching
- message passing
- fine grained
- query processing
- shared memory multiprocessors