Login / Signup
Design Techniques for a 60 Gb/s 173 mW Wireline Receiver Frontend in 65 nm CMOS Technology.
Jaeduk Han
Yue Lu
Nicholas Sutardja
Kwangmo Jung
Elad Alon
Published in:
IEEE J. Solid State Circuits (2016)
Keyphrases
</>
cmos technology
power consumption
low power
high speed
power dissipation
spl times
parallel processing
real time
case study
moving objects
low voltage