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Design Techniques for a 60 Gb/s 173 mW Wireline Receiver Frontend in 65 nm CMOS Technology.

Jaeduk HanYue LuNicholas SutardjaKwangmo JungElad Alon
Published in: IEEE J. Solid State Circuits (2016)
Keyphrases
  • cmos technology
  • power consumption
  • low power
  • high speed
  • power dissipation
  • spl times
  • parallel processing
  • real time
  • case study
  • moving objects
  • low voltage