USB Transceiver With a Serial Interface Engine and FIFO Queue for Efficient FPGA-to-FPGA Communication.
Guo-Ming SungLi-Fen TungHsin-Kwang WangJhih-Hao LinPublished in: IEEE Access (2020)
Keyphrases
- high speed
- hardware implementation
- field programmable gate array
- signal processing
- efficient implementation
- data acquisition
- low cost
- real time image processing
- hardware design
- real time
- single chip
- verilog hdl
- digital signal
- communication protocol
- user interface
- data transmission
- user friendly
- hardware architecture
- hardware architectures
- smart card
- markov chain
- fpga device
- image processing