A Low-Power Timing-Error-Tolerant Circuit by Controlling a Clock.
Isaak YangKwang-Hyun ChoPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2021)
Keyphrases
- low power
- error tolerant
- high speed
- power consumption
- logic circuits
- cmos technology
- power reduction
- graph matching
- power dissipation
- gate array
- vlsi circuits
- low cost
- delay insensitive
- subgraph isomorphism
- mixed signal
- low power consumption
- digital signal processing
- real time
- association patterns
- image sensor
- point sets
- matching algorithm
- data model