A high level implementation and performance evaluation of level-I asynchronous cache on FPGA.
Mansi JhambR. K. SharmaA. K. GuptaPublished in: J. King Saud Univ. Comput. Inf. Sci. (2017)
Keyphrases
- high level
- lower level
- hardware implementation
- higher level
- low level
- software implementation
- hardware architecture
- object level
- real time
- hardware design
- fpga implementation
- high speed
- asynchronous communication
- data access
- levels of abstraction
- knowledge level
- field programmable gate array
- database systems
- dedicated hardware
- fpga technology