A Low-power Reconfigurable Readout Circuit with Large DC Offset Reduction for Neural Signal Recording Applications.
Nishat Tarannum TasneemIfana MahbubPublished in: MWSCAS (2020)
Keyphrases
- power reduction
- low power
- power consumption
- high speed
- low cost
- high power
- signal processing
- power dissipation
- logic circuits
- network architecture
- wireless transmission
- cmos technology
- single chip
- digital signal processing
- low power consumption
- vlsi architecture
- frequency domain
- vlsi circuits
- delay insensitive
- impulse response
- power saving
- real time
- gate array
- high frequency
- embedded systems
- wireless networks
- general purpose
- wide dynamic range
- nm technology
- image processing