LDPC decoder implementation using FPGA.
Mahdie KiaeeHossein GharaeeNaser MohammadzadehPublished in: IST (2016)
Keyphrases
- fpga implementation
- hardware implementation
- low density parity check
- efficient implementation
- software implementation
- distributed video coding
- ldpc codes
- fpga technology
- distributed source coding
- turbo codes
- hardware architecture
- field programmable gate array
- low complexity
- high speed
- low cost
- parallel architecture
- computing systems
- image compression
- dedicated hardware
- motion estimation
- real time