High-performance asynchronous pipeline circuits.
Kenneth Y. YunPeter A. BeerelJulio ArceoPublished in: ASYNC (1996)
Keyphrases
- delay insensitive
- high level synthesis
- asynchronous circuits
- shift register
- parallel architecture
- high speed
- scientific computing
- high reliability
- real time
- analog circuits
- circuit design
- distributed memory
- database systems
- database
- image sequences
- case study
- small sized
- state machines
- website
- analog vlsi
- knowledge base
- pipeline architecture