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A Combined Dynamic and Static Frequency Divider for a 40GHz PLL in 80nm CMOS.

George von BürenChristian KromerFrank EllingerAlex HuberMartin L. SchmatzHeinz Jäckel
Published in: ISSCC (2006)
Keyphrases
  • power consumption
  • clock gating
  • high speed
  • dynamic analysis
  • dynamic environments
  • low power
  • dynamic constraints
  • data sets
  • circuit design
  • cmos technology