Effect of floating-point error reduction with recursive least square for parallel architecture.
Hiroshi TsubokawaHajime KubotaShigeo TsujiiPublished in: ICASSP (1990)
Keyphrases
- floating point
- error reduction
- parallel architecture
- recursive least squares
- parallel processing
- fixed point
- hardware implementation
- classification error
- floating point arithmetic
- semi supervised
- parallel implementation
- feature selection
- machine learning
- distributed memory
- significant improvement
- learning algorithm
- neural network
- neuro fuzzy
- scheduling problem
- objective function