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Symbolic synthesis of clock-gating logic for power optimization of synchronous controllers.
Luca Benini
Giovanni De Micheli
Enrico Macii
Massimo Poncino
Riccardo Scarsi
Published in:
ACM Trans. Design Autom. Electr. Syst. (1999)
Keyphrases
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power consumption
power reduction
low power
power dissipation
control system
power management
logic synthesis
energy efficiency
binary decision diagrams
pattern recognition
parallel algorithm
formal verification
chip design
clock gating