A network flow approach to memory bandwidth utilization in embedded DSP core processors.
Catherine H. GebotysPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2002)
Keyphrases
- network flow
- bandwidth utilization
- embedded processors
- linear programming
- minimum cost
- quality of service
- integer programming
- signal processing
- memory subsystem
- parallel processing
- min cost
- parallel algorithm
- optimization model
- single processor
- embedded systems
- main memory
- digital signal processor
- web services
- social networks