Enhancing Temporal Logic Falsification With Specification Transformation and Valued Booleans.
Johan Lidén EddelandKoen ClaessenNicholas SmallboneZahra RamezaniSajed MiremadiKnut ÅkessonPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2020)
Keyphrases
- temporal logic
- transition systems
- model checking
- reactive systems
- linear temporal logic
- formal specification
- concurrent systems
- modal logic
- formal verification
- satisfiability problem
- dynamic constraints
- formal methods
- verification method
- mazurkiewicz traces
- computation tree logic
- model checker
- temporal knowledge
- specification language
- formal specification language
- temporal properties
- planning problems
- bounded model checking
- belief revision
- automata theoretic
- data model