Reducing instruction bit-width for low-power VLIW architectures.
Jongwon LeeJonghee M. YounDoosan ChoYunheung PaekPublished in: ACM Trans. Design Autom. Electr. Syst. (2013)
Keyphrases
- low power
- power consumption
- low cost
- high speed
- power reduction
- level parallelism
- single chip
- high power
- memory hierarchy
- wireless transmission
- low power consumption
- logic circuits
- instruction set
- cmos technology
- image sensor
- vlsi architecture
- vlsi circuits
- general purpose
- multi core processors
- digital signal processing
- analog to digital converter
- mixed signal
- multi channel
- cmos image sensor
- nm technology