Adaptive Clock Gating Technique for Low Power IP Core in SoC Design.
Xiaotao ChangMingming ZhangGe ZhangZhimin ZhangJun WangPublished in: ISCAS (2007)
Keyphrases
- low power
- power consumption
- power dissipation
- power reduction
- single chip
- low power consumption
- low cost
- high speed
- clock gating
- digital signal processing
- logic circuits
- vlsi architecture
- cmos technology
- gate array
- nm technology
- energy efficiency
- vlsi circuits
- power saving
- ultra low power
- image processing
- mixed signal
- data center
- power management
- design process
- pattern recognition
- real time