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A Compact 20GHz Dynamic Latch Comparator in 65nm CMOS Process.

Folla Kamdem JérômeWembe Tafo EvaristeEssimbi Zobo BernardMaria Liz CrespoAndres Cicuttin
Published in: SSD (2021)
Keyphrases
  • power consumption
  • high speed
  • dynamic environments
  • clock gating
  • neural network
  • real world
  • search engine
  • dynamically changing