A 52-Gb/s Sub-1pJ/bit PAM4 Receiver in 40-nm CMOS for Low-Power Interconnects.
Can WangGuang ZhuZhao ZhangC. Patrick YuePublished in: VLSI Circuits (2019)
Keyphrases
- low power
- cmos technology
- high speed
- nm technology
- power dissipation
- low voltage
- power consumption
- low cost
- random access memory
- mixed signal
- high power
- single chip
- silicon on insulator
- analog to digital converter
- wireless transmission
- power reduction
- vlsi circuits
- logic circuits
- low power consumption
- gate array
- digital signal processing
- delay insensitive
- image sensor
- vlsi architecture
- cmos image sensor