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Design and evaluation of a high throughput QoS-aware and congestion-aware router architecture for Network-on-Chip.
Chifeng Wang
Nader Bagherzadeh
Published in:
Microprocess. Microsystems (2014)
Keyphrases
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high throughput
network on chip
microarray
power dissipation
routing algorithm
qos aware
multi processor
data acquisition
network simulator
design process
data transfer
high speed
shortest path
data center
ip networks