A reusability-aware cache memory sharing technique for high-performance low-power CMPs with private L2 caches.
Sungjune YounHyunhee KimJihong KimPublished in: ISLPED (2007)
Keyphrases
- low power
- memory access
- shared memory
- single chip
- embedded processors
- cache misses
- low power consumption
- signal processor
- low cost
- power consumption
- high speed
- main memory
- memory hierarchy
- distributed memory
- caching scheme
- memory management
- data access
- prefetching
- memory subsystem
- coarse grained
- wireless transmission
- cache hit ratio
- high power
- vlsi architecture
- external memory
- power dissipation
- logic circuits
- image sensor
- parallel algorithm
- vlsi circuits
- computing power
- multithreading
- mixed signal
- message passing
- digital signal processing
- nm technology
- embedded dram
- database management systems
- ultra low power
- cmos technology
- storage devices