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An 80MHz-BW 31.9fJ/conv-step Filtering ΔΣ ADC with a Built-In DAC-Segmentation/ELD-Compensation 6b 960MS/s SAR-Quantizer in 28nm LP for 802.11ax Applications.

Chi-Yun WangJen-Huan TsaiSheng-Yuan SuJen-Che TsaiJhy-Rong ChenChih-Hong Lou
Published in: ISSCC (2019)
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