A 6.72-Gb/s, 8pJ/bit/iteration WPAN LDPC decoder in 65nm CMOS.
Zhixiang ChenXiao PengXiongxin ZhaoLeona OkamuraDajiang ZhouSatoshi GotoPublished in: ASP-DAC (2013)
Keyphrases
- low density parity check
- ldpc codes
- nm technology
- distributed source coding
- high speed
- low power
- random access memory
- cmos technology
- turbo codes
- distributed video coding
- successive approximation
- silicon on insulator
- decoding algorithm
- compressive sensing
- power consumption
- channel coding
- analog to digital converter
- message passing
- error correction
- metal oxide semiconductor
- low complexity
- low cost
- data transmission
- source coding
- rate allocation
- error resilience
- low voltage
- random projections
- error resilient
- video codec
- error concealment
- forward error correction
- image transmission
- integrated circuit
- low rate
- power dissipation
- transform domain
- temporal correlation
- error propagation
- rate distortion
- video transmission
- video coding