Improving a design methodology of synthesizable VHDL with formal verification.
Luis Gustavo Perpetuo Costa MarquesMax Hering de QueirozJean-Marie FarinesPublished in: LASCAS (2016)
Keyphrases
- design methodology
- formal verification
- model checking
- formal specification
- physical design
- design criteria
- model checker
- automated verification
- fuzzy neural network
- object oriented
- field programmable gate array
- design process
- bounded model checking
- design methodologies
- symbolic model checking
- design procedure
- hw sw
- hardware implementation
- hardware software
- hardware description language
- database systems
- hardware design
- databases
- integrated circuit
- temporal logic
- web services