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Improvement in Retention/Program Time Ratio of Direct Tunneling Memory (DTM) for Low Power SoC Applications.
Kouji Tsunoda
Akira Sato
Hiroko Tashiro
Toshiro Nakanishi
Hitoshi Tanaka
Published in:
IEICE Trans. Electron. (2005)
Keyphrases
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low power
power consumption
low cost
high speed
single chip
power dissipation
high power
vlsi circuits
digital signal processing
logic circuits
vlsi architecture
wireless transmission
low power consumption
hardware and software
mixed signal
computational power
main memory
energy dissipation