An efficient stream memory architecture for heterogeneous multicore processor.
Rangyu DengWeixia XuQiang DouHongwei ZhouZefu DaiHaiyan ChenPublished in: ISCC (2009)
Keyphrases
- memory management
- level parallelism
- memory hierarchy
- operating system
- memory access
- instruction set
- hardware implementation
- processing elements
- memory bandwidth
- computation intensive
- computing power
- data streams
- real time
- multi core processors
- parallel architecture
- multithreading
- loosely coupled
- parallel processing
- memory subsystem
- main memory
- multi processor
- cell processor
- central processing unit
- streaming data
- high end
- memory requirements
- shared memory
- sliding window
- management system
- single processor
- computer architecture
- single instruction multiple data
- limited memory