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Low-Power Area-Efficient Fault Tolerant Adder in Current Mode Multi Valued Logic Using Berger Codes.
Shahram Mohammadi
Reza Omidi Gosheblagh
Mohammad Lotfinejad
Published in:
J. Electron. Test. (2020)
Keyphrases
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fault tolerant
low power
fault tolerance
low cost
logic circuits
power consumption
high speed
distributed systems
single chip
high power
vlsi architecture
vlsi circuits
low power consumption
low density parity check
wireless transmission
digital signal processing
power reduction
load balancing