Design space exploration for low-power channel decoder in embedded LDPC-H.264 joint decoding architecture.
Yoon Seok YangGwan ChoiPublished in: Int. J. Inf. Technol. Commun. Convergence (2011)
Keyphrases
- low density parity check
- low power
- vlsi architecture
- ldpc codes
- design space exploration
- decoding algorithm
- channel coding
- error correction
- power consumption
- distributed video coding
- low cost
- physical layer
- design space
- high speed
- message passing
- channel capacity
- unequal error protection
- turbo codes
- embedded systems
- low complexity
- design process
- image transmission
- real time
- vlsi implementation
- error propagation
- mixed signal
- forward error correction
- error resilient
- source coding
- error resilience
- bit error rate
- cmos technology
- bitstream
- rate allocation
- video transmission
- design methodology
- computing systems
- case study