A 1.7 mW 11b 250 MS/s 2-Times Interleaved Fully Dynamic Pipelined SAR ADC in 40 nm Digital CMOS.
Bob VerbruggenMasao IriguchiJan CraninckxPublished in: IEEE J. Solid State Circuits (2012)
Keyphrases
- power consumption
- power supply
- analog to digital converter
- hd video
- circuit design
- metal oxide semiconductor
- synthetic aperture radar
- cmos image sensor
- sigma delta
- dynamic range
- real time
- high speed
- low power
- sar images
- image reconstruction
- high definition
- parameter estimation
- dynamic environments
- denoising
- nm technology
- multiscale