Worst Case Timing Analysis of RISC Processors: R3000/R3010 Case Study.
Yerang HurYoung Hyun BaeSung-Soo LimSung-Kwan KimByung-Do RheeSang Lyul MinChang Yun ParkHeonshik ShinChong-Sang KimPublished in: RTSS (1995)
Keyphrases
- case study
- worst case
- instruction set
- application specific
- average case
- parallel algorithm
- upper bound
- parallel processing
- lower bound
- error bounds
- greedy algorithm
- floating point
- running times
- worst case analysis
- approximation algorithms
- software development
- np hard
- single processor
- lessons learned
- multiprocessor systems
- space complexity
- parallel computing
- real world
- mistake bound
- computer architecture
- list scheduling
- hardware architecture
- high performance computing
- embedded systems
- development process
- business process
- multi class