An Efficient I/O Architecture for RAM-Based Content-Addressable Memory on FPGA.
Xuan-Thuan NguyenTrong-Thuc HoangHong-Thu NguyenKatsumi InoueCong-Kha PhamPublished in: IEEE Trans. Circuits Syst. II Express Briefs (2019)
Keyphrases
- content addressable memory
- high speed
- hardware architecture
- hardware implementation
- real time
- dedicated hardware
- fpga implementation
- design considerations
- main memory
- software implementation
- hardware design
- field programmable gate array
- parallel architecture
- memory access
- xilinx virtex
- pipelined architecture
- fpga technology
- hardware architectures
- neural network
- data flow
- file system
- efficient implementation
- signal processing
- image processing