A Power-Efficient 10T D Flip-Flop with Dual Line of Four Switches using 65nm CMOS Technology.

Elim Lee Youngmin Kim

Published in: ISOCC (2023)

Keyphrases

cmos technology
power consumption
power dissipation
low power
flip flops
spl times
silicon on insulator
low voltage
low cost
digital signal processing
parallel processing
high speed