A customizable FPGA IP core implementation of a general purpose Genetic Algorithm engine.
Pradeep FernandoHariharan SankaranSrinivas KatkooriDidier KeymeulenAdrian StoicaRicardo Salem ZebulumRajeshuni RameshamPublished in: IPDPS (2008)
Keyphrases
- general purpose
- genetic algorithm
- hardware implementation
- highly optimized
- high speed
- fitness function
- multi objective
- general purpose processors
- hardware design
- special purpose
- signal processing
- domain specific
- efficient implementation
- neural network
- population size
- hardware architecture
- real time image processing
- artificial neural networks
- data acquisition
- parallel architecture
- software implementation
- information systems
- dedicated hardware
- fpga hardware