Low power instruction cache design based on branch execution tracks.

Quanquan Li Qi Wang Tiejun Zhang Donghui Wang Chaohuan Hou

Published in: ASICON (2013)

Keyphrases

low power
power consumption
single chip
high speed
low cost
low power consumption
logic circuits
vlsi architecture
memory hierarchy
digital signal processing
power dissipation
design process
gate array
high power
mixed signal
wireless transmission
cmos technology
power reduction
design methodology