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A Prototype-Based Gate-Level Cycle-Accurate Methodology for SoC Performance Exploration and Estimation.
Ching-Lung Su
Tse-Min Chen
Kuo-Hsuan Wu
Published in:
VLSI Design (2013)
Keyphrases
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accurate estimation
levels of abstraction
error analysis
highly accurate
test bed
estimation algorithm
multiscale
computationally efficient
hardware and software
density estimation
neural network
higher level
high accuracy
high quality
case study
metadata
genetic algorithm
data mining