CASSANN-v2: A high-performance CNN accelerator architecture with on-chip memory self-adaptive tuning.
Feng LiuRuixiu QiaoGang ChenGuoliang GongHuaxiang LuPublished in: IEICE Electron. Express (2022)
Keyphrases
- embedded dram
- random access memory
- compute intensive
- level parallelism
- memory access
- memory subsystem
- multithreading
- signal processor
- physical design
- digital signal processors
- cellular neural networks
- analog vlsi
- vlsi implementation
- parallel computers
- real time
- host computer
- hardware architectures
- management system
- computational power
- low cost
- high speed
- design considerations
- field programmable gate array
- parallel implementation
- neural network
- memory requirements
- cmos technology
- parallel computing
- memory bandwidth
- low power consumption
- low power
- cmos image sensor
- high bandwidth
- nm technology
- computing platform