A Memory-Efficient Hardware Architecture for Deformable Convolutional Networks.
Yue YuJiapeng LuoWendong MaoZhongfeng WangPublished in: SiPS (2021)
Keyphrases
- memory efficient
- hardware architecture
- hardware implementation
- hardware architectures
- external memory
- associative memory
- social networks
- multiple sequence alignment
- computer vision
- iterative deepening
- field programmable gate array
- efficient implementation
- network structure
- video coding
- signal processing
- pattern recognition
- case study
- block matching motion estimation