Parallel turbo-sum-product decoder architecture for quasi-cyclic LDPC codes.
Yongmei DaiZhiyuan YanNing ChenPublished in: ACM Great Lakes Symposium on VLSI (2006)
Keyphrases
- ldpc codes
- sum product
- message passing
- error correction
- decoding algorithm
- turbo codes
- low density parity check
- rate allocation
- channel coding
- image transmission
- belief propagation
- forward error correction
- low complexity
- source coding
- distributed systems
- graphical models
- markov random field
- post processing
- graph cuts