Chaotic encoder-decoder on FPGA for crypto system.
Chanathip RoeksukrungrueangXaysamone DittaphongKhamphong KhongsomboonNounchan PanyanouyongSorawat ChivapreechaPublished in: APSIPA (2014)
Keyphrases
- video codec
- video decoder
- decoding process
- distributed video coding
- fpga implementation
- low complexity
- low power consumption
- wyner ziv
- error control
- video coding
- noisy channel
- successive approximation
- distributed source coding
- rate distortion
- video coding scheme
- wyner ziv video coding
- mpeg avc
- power reduction
- motion compensated prediction
- hardware implementation
- transform domain
- low cost
- field programmable gate array
- motion estimation
- high speed
- motion compensation
- video quality
- error resilience
- turbo codes
- video encoder
- inter frame
- rate allocation
- compressed video
- power consumption
- video compression
- source coding
- low power
- temporal correlation
- bit budget
- bit rate
- low bit rate
- motion compensated
- vector quantization
- compressive sensing
- error correction
- video transcoding
- bit rate reduction
- error resilient
- security protocols
- coding scheme
- pixel domain
- mode decision
- video coding standard
- video transmission
- bit plane
- motion vectors
- signal processing
- computational complexity