A low power UART design based on asynchronous techniques.
Dipanjan BhadraVikas S. VijKenneth S. StevensPublished in: MWSCAS (2013)
Keyphrases
- low power
- single chip
- power consumption
- low cost
- logic circuits
- low power consumption
- high speed
- gate array
- digital signal processing
- mixed signal
- vlsi architecture
- delay insensitive
- vlsi circuits
- design process
- ultra low power
- power dissipation
- image processing
- long range
- wireless transmission
- power reduction
- cmos image sensor
- nm technology