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A Compact AES Hardware Implementation Secure Against 1st-Order Side-Channel Attacks.

Qian ZhangYongbin ZhouShuang QiuWei ChengJingdian MingRui Zhang
Published in: ICCD (2018)
Keyphrases
  • hardware implementation
  • efficient implementation
  • feature selection
  • neural network
  • block cipher
  • pipeline architecture
  • high speed
  • parallel architecture