A 65-nm CMOS 7fJ per synaptic event clique-based neural network in scalable architecture.
Benoit LarrasPaul CholletCyril LahuecFabrice SeguinMatthieu ArzelPublished in: ISCAS (2017)
Keyphrases
- neural network
- cmos technology
- network architecture
- feed forward
- nm technology
- low power
- neural architecture
- event driven
- analog vlsi
- artificial neural networks
- neuron model
- multi layer
- learning rules
- power consumption
- real time
- scalable distributed
- back propagation
- event detection
- high speed
- hd video
- bp neural network
- fuzzy logic
- neural network model
- low cost
- feed forward neural networks
- design methodology
- publish subscribe
- management system
- hebbian learning
- associative memory
- software architecture