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High-Speed FPGA-to-FPGA Interface for a Multi-Chip CNN Accelerator.

Gitae ParkThaising TaingHyungwon Kim
Published in: ISOCC (2023)
Keyphrases
  • high speed
  • field programmable gate array
  • low power
  • data acquisition
  • gigabit ethernet
  • real time
  • low cost
  • single chip
  • hardware implementation
  • high speed networks
  • user friendly
  • low power consumption
  • power reduction