A 353pW, 0.014%/V line sensitivity self-biased CMOS voltage reference with source degeneration active load.

Kai Yu Jingran Zhang Sizhen Li

Published in: IEICE Electron. Express (2024)

Keyphrases

low voltage
power supply
design considerations
electrical power
random access memory
cmos technology
power management
high speed
reactive power
sensitivity analysis
high quality
low power
power system
low cost
load balancing
transmission line
power network
computational intelligence
active power
neural network