A 48-16-MHz CMOS SC decimation filter.

Fernando Antonio Pinto Barúqui Antonio Petraglia José E. Franca

Published in: IEEE J. Solid State Circuits (2002)

Keyphrases

high speed
cmos technology
low pass filter
low cost
low power
noise reduction
nm technology
analog vlsi
power supply
power consumption
neural network
parallel processing
high frequency
image processing
transfer function
signal to noise ratio
delay insensitive
wavelet transform
frequency domain analysis