The design of a 1.5 V, 10-bit, 10 M samples/s low power pipelined analog-to-digital converter.
Jen-Shiun ChiangMing-Da ChiangPublished in: ISCAS (2000)
Keyphrases
- analog to digital converter
- low power
- mixed signal
- delta sigma
- low cost
- high speed
- single chip
- image sensor
- power consumption
- vlsi architecture
- low power consumption
- logic circuits
- cmos technology
- digital signal processing
- gate array
- power dissipation
- real time
- multi channel
- hardware and software
- cmos image sensor
- digital camera
- parallel processing
- ultra low power
- image processing