CHO: towards a benchmark suite for OpenCL FPGA accelerators.
Geoffrey NduJavier NavaridasMikel LujánPublished in: IWOCL (2015)
Keyphrases
- benchmark suite
- field programmable gate array
- hardware implementation
- parallel computing
- embedded systems
- single chip
- image processing algorithms
- fpga implementation
- computing systems
- graphics processing units
- transactional memory
- hardware architecture
- hardware design
- fpga technology
- parallel programming
- hardware software
- parallel architectures
- software implementation
- massively parallel
- fpga device
- high end
- low power consumption
- reconfigurable hardware
- shared memory
- computer systems
- signal processing
- low cost
- low power
- xilinx virtex