Hardware Implementation of AES Using Area-Optimal Polynomials for Composite-Field Representation GF(2^4)^2 of GF(2^8).
Shay GueronSanu MathewPublished in: ARITH (2016)
Keyphrases
- hardware implementation
- efficient implementation
- software implementation
- dedicated hardware
- hardware architecture
- field programmable gate array
- pipeline architecture
- real time
- signal processing
- optimal solution
- dynamic programming
- hardware design
- fpga implementation
- image processing algorithms
- general purpose
- memory management
- machine learning
- data mining
- pattern recognition
- data structure
- image processing
- fpga technology