Fast Multiplier Generator for FPGAs with LUT based Partial Product Generation and Column/row Compression.
Ahmet KakacakAydin Emre GuzelOzan CihangirSezer GörenH. Fatih UgurdagPublished in: Integr. (2017)
Keyphrases
- hardware implementation
- lookup table
- binary matrices
- binary matrix
- rows and columns
- data compression
- data matrix
- life cycle
- generation process
- compression algorithm
- field programmable gate array
- compression scheme
- product design
- product quality
- product information
- random access
- compressed data
- floating point
- hardware software
- image compression