A Pipelined Parallel Processor to Implement MD4 Message Digest Algorithm on Xilinx FPGA.
M. Bhaskar SherigarA. S. MahadevanK. Senthil KumarDavid S. SumamPublished in: VLSI Design (1998)
Keyphrases
- parallel processors
- hardware implementation
- fpga implementation
- learning algorithm
- pipelined architecture
- hardware architecture
- cost function
- dynamic programming
- high speed
- probabilistic model
- combinatorial optimization
- np hard
- search space
- worst case
- field programmable gate array
- reinforcement learning
- genetic algorithm