A comparative study on the implementation of reversible Binary Coded Decimal (BCD) Adder performance on Field Programmable Gate array (FPGA).
Nyap Tet Clement ThamAlpha Agape GopalaiLenin GopalAshutosh Kumar SinghPublished in: ICCSCE (2014)
Keyphrases
- field programmable gate array
- hardware implementation
- fpga technology
- fpga device
- hardware architecture
- xilinx virtex
- software implementation
- reconfigurable hardware
- fpga implementation
- hardware design
- embedded systems
- hardware software co design
- image processing algorithms
- programmable logic
- parallel computing
- hardware software
- digital signal processors
- computing systems
- pipelined architecture
- efficient implementation
- hardware and software
- hardware description language
- digital signal processing
- floating point
- processing elements
- massively parallel
- host computer
- real time
- general purpose processors
- high end
- high speed